Job Description:
- Timing Closure Fixing.
- DFT expert (SCAN/ATPG/ MBIST/BSCAN/MBISR/At-Speed).
- Hierarchical Experience is preferred for 100M+ gate count.
- CAD tool evaluation and consultant for frontend implementation
Requirements:
- At least 3 years of relevant work experience.
- Intermediate proficiency in English.
其他條件:
- MS in EE or CS.
- Familiar with IC design flow (SYN/STA/DFT/Low power . . .).
- Familiar with EDA tools (Synopsys DC/DCG/PT/Tweaker/vclp . . .).
- Familiar with shell/TCL/Perl/Python is a plus.
- Experience in FinFET process or huge SoC/hierarchical design is a plus.
Location: 新竹縣竹北市 (台元科技園區)
