Job Description:

  • Ongoing project R2G synthesis (top down/button up).
  • Logic equivalent check with R2G/G2G.
  • Pre netlist timing closure.
  • Synthesis flow maintenance.

Requirements:

  • At least 3 years of relevant work experience.
  • Intermediate proficiency in English.
  • With Digital design synthesis ability.
  • With Formal verification ability (R2G / G2G).
  • With timing analysis and closure ability.
  • With Shell/TCL language ability.
  • DCT/DCG is a plus.
  • Hierarchical Synthesis is a plus.
  • Low power cell insert / debug in DC is a plus.
  • DFT structure insert in DC is a plus.
  • EDA tool: Design compiler, Formality, Primetime, VCLP, the more the better.

Location: 新竹縣竹北市 (台元科技園區)