Job Description:

  • DFT planning & implementation for MBIST/SCAN/ATPG/BSCAN…
  • Perform STA & timing closure for DFT modes.
  • Create DFT test pattern & perform DFT Verilog simulation.
  • Co-work with Test Engineers to bring-up testing in ATE.

Requirements:

  • At least 3 years of relevant work experience.
  • Intermediate proficiency in English.
  • Familiar with DFT flow development(MBIST/SCAN/ATPG/BSCAN/LBIST).
  • Familiar with DFT realted flow and EDA tools(e.g. compiler, TetraMax, Tessent & Test Kompress).
  • Familiar with IC design flow(e.g. verilog/RTL/STA/LEC/Simulation flow).
  • Proficient in Unix Shell/Tcl/Perl & programming skills.
  • 14nm/7nm & million-gate SOC design experience is a plus.

Location: 新竹縣竹北市 (台元科技園區)